Notes from the project
Setup details, failures, workarounds, and measurements after their sources and wording have been reviewed.
DFlash & DFlash2: Block Diffusion LLM Speedup
Local LLM inference rarely bottlenecks on matrix compute—it chokes on memory bandwidth, capping 70B models below 16 tokens/s on 608 GB/s GDDR6. DFlash2 eliminates this sequential memory wall through parallel block diffusion, tripling decode throughput on Intel Arc and modern workstations with zero mathematical precision loss across vLLM and SGLang.
Intel Arc Pro B65: specifications in context
Intel lists 32 GB of GDDR6 and 608 GB/s for the Arc Pro B65. This overview separates the GPU specification from board details and measured inference performance.
SGLang v0.5.15.post1: DSA launch and GLM-5.2 fixes
The SGLang v0.5.15.post1 patch covers DSA model startup, CUDA image dependencies and GLM-5.2 fixes. A closer look at the corrected CuTe DSL import.
SGLang v0.5.15: XPU graphs and speculative decoding
SGLang v0.5.15 brings XPU graph and speculative-decoding work. The upstream changes also document a graph-capture limitation in the Intel test backend.
SGLang v0.5.14: XPU and prefix-cache changes
A look at SGLang v0.5.14: the Intel XPU mRoPE path, PyTorch dependency update, and optional INT8 checkpoints for linear-attention prefix reuse.